CTCNT=0, CTAS=000, EOQ=0, PCS=0, CONT=0
DSPI PUSH TX FIFO Register In Master Mode
TXDATA | Transmit Data |
PCS | Select which PCS signals are to be asserted for the transfer 0 (0): Negate the PCS[x] signal. 1 (1): Assert the PCS[x] signal. |
CTCNT | Clear Transfer Counter. 0 (0): Do not clear the TCR[SPI_TCNT] field. 1 (1): Clear the TCR[SPI_TCNT] field. |
EOQ | End Of Queue 0 (0): The SPI data is not the last data to transfer. 1 (1): The SPI data is the last data to transfer. |
CTAS | Clock and Transfer Attributes Select. 0 (000): CTAR0 1 (001): CTAR1 |
CONT | Continuous Peripheral Chip Select Enable 0 (0): Return PCSn signals to their inactive state between transfers. 1 (1): Keep PCSn signals asserted between transfers. |